module top(clkin, clkout, i, dtack, as);

input	clkin, as;
input	[2:0]i;
output	clkout, dtack;
wire	wclock;
assign wclock = clkout;

clockosc u1(.clkin(clkin), .clkout(clkout));
dtackgen u2(.clk(wclock), .j(i), .dtack(dtack), .as(as));

endmodule
